Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates or trapping layers or other physical phenomena, determine the data state of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a logical column of memory cells is coupled in parallel with each memory cell coupled to a data line, such as those typically referred to as digit (e.g., bit) lines. In NAND flash architecture, a column of memory cells is coupled in series with only the first memory cell of the column coupled to a bit line.
Content addressable memories (CAM) are memories that implement a lookup table function in a single clock cycle. They use dedicated comparison circuitry to perform the lookups. CAM application are often used in network routers for packet forwarding and the like. Each individual memory bit in a CAM requires its own comparison circuit in order to allow the CAM to detect a match between a bit of the key word (e.g., pattern) with a bit stored in the CAM. Typical CAM cells, then, use approximately nine to ten transistors for a static random access memory (SRAM)-based CAM, or four to five transistors for a dynamic random access memory (DRAM)-based CAM.
In a two cell NAND CAM, one bit of data is stored in a pair of cells, each cell being programmed to one of at least two data states (S0, S1). One bit of a pattern is coded as two read voltages on word lines (Vr0, Vr1) of the pair of cells. A combination of read voltages and cell states is used to determine a match/no-match condition for a bit, e.g., when the bit of the pattern is concordant with the data of a cell pair (e.g., cell pair does not conduct), a match may be indicated, and when the bit of the pattern is opposite of the data of the cell pair (e.g., cell pair conducts), a no-match condition may be indicated. Pass voltages are used to remove cell pairs in a string that are not to be part of a match operation, e.g., cause these cell pairs to conduct regardless of their data states. Typically, a determination of a match/no-match condition for a data pattern will examine a plurality of cell pairs connected in parallel to a bit line. If all cell pairs under examination match, then no conduction will be present on the bit line (e.g., a precharged data line), which will not discharge, indicating a match for the cell pairs under examination. If any cell pair under examination does not match, e.g., both cells of at least one cell pair conduct, the bit line (e.g., a precharged data line) is discharged, indicating a no-match condition.
FIG. 1 shows a basic two cell NAND CAM. Such a CAM is described in greater detail in U.S. patent application Ser. No. 13/449,082, filed Apr. 17, 2012, titled “METHODS AND APPARATUS FOR PATTERN MATCHING”. In a two cell NAND CAM 100, one bit of data can be stored as threshold voltages (representing data states) in two cells, 102 and 104. A logical 0 value for a bit of data programmed into two cells 102 and 104 can be represented by a first threshold voltage of 3 volts (e.g., within the data state 51) on the first cell (e.g., cell 102) and a second threshold voltage of 1 volt (e.g., within the data state S0) on the second cell (e.g., cell 104), and a logical 1 value for a bit of data programmed into two cells can be represented by a first threshold voltage of 1 volt (e.g., within the data state S0) on the first cell (e.g., cell 102) and a second threshold voltage of 3 volts (e.g., within the data state 51) on the second cell (e.g., cell 104). Although specific voltage levels are provided herein for ease of understanding, they are merely examples and may vary depending upon the particular memory technology utilized and other operation parameters.
A pattern to be matched in the memory is stored or received as well. Each bit of the pattern to be matched is represented by two voltages on word lines (e.g., Vr0 and Vr1). For example, a logical 0 value for a pattern bit may cause a voltage of 2 volts (e.g., Vr0, a voltage sufficient to activate a cell having the S0 data state but not activate a cell having the 51 data state) to be applied to the gate of the first cell (e.g., cell 102) of the two cells, and may cause a voltage of 4 volts (e.g., Vr1, a voltage sufficient to activate a cell having the 51 data state) to be applied to the gate of the second cell (e.g., cell 104) of the two cells. A logical 1 value for a pattern bit may cause a voltage of 4 volts (e.g., a voltage sufficient to activate a cell having the 51 data state) to be applied to the gate of the first cell (e.g., cell 102) of the two cells, and may cause a voltage of 2 volts (e.g., a voltage sufficient to activate a cell having the S0 data state but not activate a cell having the 51 data state) to be applied to the gate of the second cell (e.g., cell 104) of the two cells. A comparison is made to a representation of data stored in the array, where each bit of stored data is also represented by two cells, each having its own programmed threshold voltage. A register may be used to store the pattern of bits, e.g., two bits of the register for each bit of the pattern.
With these threshold voltages and word line voltages, a no-match between the data stored in the cells 102 and 104 is determined when both cells conduct, and the bit line (e.g., precharged data line) for those cells discharges. When at least one cell does not conduct, a match condition is determined. FIG. 2 shows basic no-match 202 and match 204 conditions for a two cell NAND CAM. For the example of FIG. 2, cell 102 has the S0 data state and cell 104 has the S1 data state. As such, if voltage Vr0 is applied to word line WL0 and voltage Vr1 is applied to word line WL1, both cells 102 and 104 conduct as each voltage is sufficient to activate its respective cell 102 or 104. Conversely, if voltage Vr1 is applied to word line WL0 and voltage Vr0 is applied to word line WL1, cell 104 does not conduct as the voltage Vr0 is insufficient to activate cell 104. Although cell 102 would be activated in this situation, the cell pair 102/104 does not conduct as a result of their series connection.
A false match condition in NAND CAM cells can be a critical issue. A false match occurs when a cell that should be conducting moves to being a non-conducting cell. NAND memory has some inherent reliability issues. In a situation where pattern matching as in a NAND CAM memory is being performed, the reliability of NAND memory limits its application.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for increased reliability of NAND CAM memories.